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An analogy is that of a traffic jam in road networks where each car waits for the car in front of it to move, but no car can move if they end up forming a cycle.The traditional approaches to avoid deadlocks either restricts routes (leading to lower performance) or adds more queues (leading to more area and power).
Unfortunately, paying one of these two expenses is unavoidable today since a deadlock can bring the whole system to a standstill and has to be avoided for functional correctness of any interconnection network.
In this paper, Krishna and his co-authors challenge the theoretical notion of viewing deadlocks as a resource (in this case queues) dependence problem, and view it instead as a lack of coordination between distributed packets.
In their paper, Krishna and his students address this issue by adding lightweight, non-blocking, and reconfigurable interconnects within a DNN accelerator called MAERI.
They demonstrate that almost any DNN model can be mapped while utilizing close to 100 percent of the accelerator’s compute resources, by simply reconfiguring the proposed interconnects appropriately.
Gratz’s paper titled “Synchronized Progress in Interconnection Networks (SPIN) : A New Theory for Deadlock Freedom” was selected for The IEEE Micro Top Picks in Architecture for 2018.
This issue collects the year’s most significant research papers in computer architecture based on novelty and potential for long-term impact. Gratz’s paper here: “IEEE Micro Top Paper Pick 2018 – Gratz Synchronized Progress in Interconnection Networks (SPIN) A New Theory for Deadlock Freedom”.This was the first work to show a deadlock-free interconnection network with fully adaptive routing, without any routing restrictions, with only a single queue at every router port. Deep Neural Networks (DNN) have demonstrated highly promising results across applications like computer vision, speech recognition, language translation, recommendation systems, and games.Honorable Mention Krishna’s paper that was selected as an Honorable Mention is entitled “MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects.” The paper was published at the 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), held March 24-28, 2018 in Williamsburg, Virginia. The computational complexity of DNNs and a need for high energy-efficiency has led to a surge in research on hardware accelerators.The International Conference on Information and Computer Technologies (ICICT), is an anual conference hold each year in United States.It is an international forum for academia and industries to exchange visions and ideas in the state of the art and practice of information and computer technologies.These AI accelerators are designed for keeping the target DNN algorithm in mind, and use custom datapaths and memory hierarchies to provide 10-1000x better performance or energy-efficiency than traditional CPUs and GPUs.Almost every major company today is building its own version of an AI accelerator.A key challenge in designing the interconnection network connecting these processors is that of “deadlocks”.A deadlock is a scenario where a set of packets is stuck indefinitely and cannot move forward because they form a cyclic dependence.Top Pick, and another paper was selected as an Honorable Mention.Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. Every year, publishes this special issue, which recognizes the year’s top papers that have potential for long-term impact.